The disclosure relates to a display device, and more particularly to a display device having different display modes.
FIG. 1a is a schematic diagram of a conventional display panel. Display panels generally have an aspect ratio of 4:3, consistent with television standards, such as those of the national television system committee (NTSC) or phase alternating line (PAL). In recent years, HDTV (High-Definition Television) systems using an aspect ratio of 16:9, as shown in FIG. 1b, have been widely adopted.
However, HDTV display devices are more expensive than conventional display devices with aspect ratio of 4:3. Many conventional methods are utilized to display a 16:9 image on a 4:3 panel. FIG. 1c shows a schematic diagram of a conventional display result. A 16:9 image is displayed in the center display region 14 of a panel. Display regions 12 and 16 are black. Non-display regions 10a and 10b fulfil no display function, thus the drivers of the panel can be disposed thereon.
Generally panels comprise formed by interlacing data electrodes and gate electrodes. Each interlacing data electrode and gate electrode controls a display unit. A controller controls a display unit according to corresponding data and gate electrodes. Non-display regions 10a and 10b also comprise gate electrodes. However, non-display regions 10a and 10b cannot display images, and thus comprise no the corresponding display units.
FIGS. 2a and 2b are timing charts of operation of a conventional driver. Drivers shown respectively output vertical clock signals CKV(4:3) and CKV(16:9). Image data is output from output terminals Data(4:3) or Data(16:9) of the driver.
As shown in FIG. 2a, when a 4:3 panel displays a 4:3 image, the driver outputs a vertical clock signal CKV(4:3) to activate gate electrodes in the panel. As shown in FIG. 1c, the gate electrodes in non-display region 10a are sequentially activated during period t1. Since non-display region 10a cannot display images, output terminals Data(16:9) do not provide image data thereto.
During period t2, the gate electrodes in display regions 12, 14, and 16 are sequentially activated. Since the display regions 12, 14, and 16 display images, the output terminals Data(16:9) provide normal image data n thereto.
During period t3, gate electrodes in non-display region 10b are activated. Since non-display region 10a cannot display image, the output terminals Data(16:9) do not provide image data thereto.
As shown in FIG. 2b, when a 4:3 panel displays a 16:9 image, the gate electrodes in non-display region 10a are activated by the vertical clock signal CKV(16:9) during period t4. Since non-display region 10a cannot display images, output terminals Data(16:9) do not provide image data thereto.
During period t5, the gate electrodes in display region 12 are activated. The output terminal Data(16:9) provides black image data b thereto.
During period t6, the gate electrodes in display region 14 are activated and the output terminals Data(16:9) provide normal image data n thereto.
During period t7, the gate electrodes in display region 16 are activated and the output terminals Data(16:9) provide black image data b thereto.
During period t8, the gate electrodes in non-display region 10b are activated and the output terminals Data(16:9) provide no image data thereto.
The period during which a 4:3 panel displays a 16:9 image equals the period during which a 4:3 panel displays a 4:3 image. Therefore, the sum of periods t1, t2, t3 equals the sum of periods t4, t5, t6, t7, t8. Since display times of image data of 16:9 and 4:3 are the same, the period t2 equals the period t6.
If the sum of periods t4 and t5 equals period t1 and the sum of periods t7 and t8 equals period t3, as the 4:3 panel displays the 16:9 image, the controller must activate the gate electrodes in non-display region 10a and display region 12 during period t1. As the 4:3 panel displays the 4:3 image, the controller must activate the gate electrodes in non-display region 10a during period t1. Therefore, during period t1, when the 16:9 image is displayed on the 4:3 panel, the sum of the activated gate electrodes exceeds that of the gate activated electrodes when the 4:3 image is displayed on the 4:3 panel.
Similarly, as the 4:3 panel displays the 16:9 image, the controller must activate the gate electrodes in the display region 16 and non-display region 10b during period t3. If the 4:3 panel displays the 4:3 image, the controller must activate the gate electrodes in non-display region 10b during period t3. Therefore, during period t3, when the 16:9 image is displayed on the 4:3 panel, the number of activated gate electrodes exceeds that of the gate activated electrodes when the 4:3 image is displayed on the 4:3 panel.
Therefore, when the 16:9 image is displayed on the 4:3 panel, the controller must reduce the activation period of each gate electrode in non-display region 10a and display region 12 or in display region 16 and non-display region 10b, or increase the frequency of the vertical clock signal CKV, to activate all gate electrodes in non-display region 10a and display region 12 or in display region 16 and non-display region 10b for a fixed duration.
When the activation period of each gate electrode in display regions 12 and 14 is reduced and the panel is amorphous silicon, the store capacitors of the display units on the panel cannot store sufficient electric charges. A conventional solution increases the size of the thin film transistor (TFT) in the display units such that the aperture ratio and the brightness of panel are reduced, resulting in black image displayed in the display regions 12 and 14 having insufficient blackness.